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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 2000 jan 13 integrated circuits SAB9079hs multistandard picture-in-picture (pip) controller
2000 jan 13 2 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs features suitable for single pip, double window and multi pip applications data formats 4 : 1 : 1 (all modes) and 4:2:2 (most modes) sample rate of 14 mhz, 720 y*-pixels/line horizontal reduction factors 1 1 3 4 , 2 3 , 1 2 , 1 3 , 1 4 and 1 6 vertical reduction factors 1 1 , 1 2 , 1 3 and 1 4 pip osd for the sub channels displayed detection of pal/ntsc with overrule bit cte/lte like circuits in display part replay with definable auto increment, picture sample rate and picture number auto wrap programmable y*uv to rgb conversion matrix with independent coefficients for ntsc and pal sources display clock and synchronisation are derived from the main pll three 8-bit digital-to-analog converters (dacs) three 8-bit analog-to-digital converters (adcs) (7-bit performance) with clamp circuit for each acquisition channel main and sub can write to the same vdram address spaces under certain conditions; the reduction factors should be the same y* and uv pedestals on the acquisition sides independent vertical filtering with 1 : 1 for uv and y* at the display part. general description the SAB9079hs is a pip controller for a multistandard application environment in combination with a multistandard decoder such as for example tda8310, tda9143 or tda9321h. the SAB9079hs inserts one or two live video signals with reduced sizes into the main/display video signal. all video signals are expected to be analog baseband signals. the analog signals are stripped signals without sync. therefore the luminance signal is referred to as y*. the conversion into the digital environment and back is done on-chip as well as the internal clock generation. the SAB9079hs is suitable for single pip, double window and multi pip applications. ordering information type number package name description version SAB9079hs sqfp128 plastic shrink quad ?at package; 128 leads (lead length 1.6 mm); body 14 20 2.72 mm sot387-3
2000 jan 13 3 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs quick reference data symbol parameter conditions min. typ. max. unit supplies v ddd(c) digital supply voltage for the core 3.0 3.3 3.6 v v ddd(p) digital supply voltage for the periphery 4.5 5.0 5.5 v v dda analog supply voltage 3.0 3.3 3.6 v i ddd(c) digital supply current for the core tbf 115 tbf ma i ddd(p) digital supply current for the periphery tbf 10 tbf ma i dda analog supply current - 170 210 ma pll f osc oscillator frequency 3584 hsync - 56 - mhz f sys system frequency 1792 hsync - 28 - mhz 896 hsync - 14 - mhz 448 hsync - 7 - mhz b loop loop bandwidth - 4 - khz t jitter short term stability jitter during 64 m s -- 4ns z damping factor - 0.7 -
2000 jan 13 4 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... block diagram handbook, full pagewidth mgs386 SAB9079hs i 2 c-bus control clamp and adc vdram control and (re-)formatting sy 105 su 103 sv 101 pll and clock generator v bias(sa) 104 v ref(t)(sa) 107 v ref(b)(sa) 106 clamp and adc my 126 mu 128 mv 2 pll and clock generator pll and clock generator horizontal and vertical filter line memory horizontal and vertical filter dac and buffer display control line memory line memory test control mhsync 9 dvsync mvsync 21 n.c. 84 dfb 19 v ref(t)(da) 25 v ref(b)(da) 26 v bias(da) 28 dv 29 du 27 dy 24 dhsync 20 8 shsync 94 svsync 95 v bias(ma) 127 v ref(t)(ma) 124 125 v ref(b)(ma) 111 114 tcbr a0 110 115 tcbd sda 97 112 116 tcbc scl 117 tsmsb por 121 tm0 120 tm2 119 tm1 118 tc 7 tmclk 15, 18, 22, 85, 88, 109, 122 v ddd(c1) to v ddd(c7) 16, 17, 23, 86, 87, 108, 123 v ssd(c1) to v ssd(c7) 13, 47, 63, 75, 90 v ssd(p1) to v ssd(p5) 14, 48, 62, 76, 89 v ddd(p1) to v ddd(p5) 98 tsext 78 70 77 40 51 sc 79 to 83, 74 to 71 ad8 to ad0 41 to 46, 49, 50, 69, 67, 65, 61, 59, 57, 55, 53 dao0 to dao15 39 to 32, 68, 66, 64, 60, 58, 56, 54, 52 dai0 to dai15 30 v ssa(da) 31 v dda(da) 113 v ddd(p) 1 v dda(mf) 3 v ssa(ma) 4 v dda(ma) 10 v dda(mp) 11 v ssa(mp) 12 v dda(mh) 99 v dda(sa) 100 v ssa(sa) 102 v dda(sf) 91 v dda(sh) 92 v ssa(sp) 93 v dda(sp) 6 tmmsb 5 tmext 96 tsclk cas we ras dt fig.1 block diagram.
2000 jan 13 5 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs pinning symbol pin i/o description v dda(mf) 1 s analog supply voltage for main channel front-end (3.3 v) mv 2 i analog v input of main channel v ssa(ma) 3 s analog ground for main channel adcs v dda(ma) 4 s analog supply voltage for main channel adcs (3.3 v) tmext 5 i set main pll input for external mode (cmos levels) tmmsb 6 o test main msb output of pll counter (cmos levels) tmclk 7 i test clock main input (cmos levels) mvsync 8 i vertical sync input for main channel (cmos levels with hysteresis) mhsync 9 i horizontal sync input for main channel (cmos levels with hysteresis) v dda(mp) 10 s analog supply voltage for main channel pll (3.3 v) v ssa(mp) 11 s analog ground for main channel pll v dda(mh) 12 s supply of main hsync input (5.0 v) v ssd(p1) 13 s digital ground 1 for periphery; note 1 v ddd(p1) 14 s digital supply voltage 1 for periphery (5.0 v); note 2 v ddd(c1) 15 s digital supply voltage 1 for core (3.3 v); note 3 v ssd(c1) 16 s digital ground 1 for core; note 4 v ssd(c2) 17 s digital ground 2 for core; note 4 v ddd(c2) 18 s digital supply voltage 2 for core (3.3 v); note 3 dfb 19 o fast blanking control output (cmos levels) dhsync 20 o horizontal sync output (cmos levels) dvsync 21 o vertical sync output (cmos levels) v ddd(c3) 22 s digital supply voltage 3 for core (3.3 v); note 3 v ssd(c3) 23 s digital ground 3 for core; note 4 dy 24 o analog y* output of dac v ref(t)(da) 25 i/o analog top reference for dacs v ref(b)(da) 26 i/o analog bottom reference for dacs du 27 o analog u output of dac v bias(da) 28 i/o analog voltage reference dacs dv 29 o analog v output of dac v ssa(da) 30 s analog ground for dacs v dda(da) 31 s analog supply voltage for dacs (3.3 v) dai7 32 i memory input data bit 7 (cmos levels) dai6 33 i memory input data bit 6 (cmos levels) dai5 34 i memory input data bit 5 (cmos levels) dai4 35 i memory input data bit 4 (cmos levels) dai3 36 i memory input data bit 3 (cmos levels) dai2 37 i memory input data bit 2 (cmos levels) dai1 38 i memory input data bit 1 (cmos levels) dai0 39 i memory input data bit 0 (cmos levels) dt 40 o memory data transfer (cmos levels)
2000 jan 13 6 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs dao0 41 o memory output data bit 0 (cmos levels) dao1 42 o memory output data bit 1 (cmos levels) dao2 43 o memory output data bit 2 (cmos levels) dao3 44 o memory output data bit 3 (cmos levels) dao4 45 o memory output data bit 4 (cmos levels) dao5 46 o memory output data bit 5 (cmos levels) v ssd(p2) 47 s digital ground 2 for periphery; note 1 v ddd(p2) 48 s digital supply voltage 2 for periphery (5.0 v); note 2 dao6 49 o memory output data bit 6 (cmos levels) dao7 50 o memory output data bit 7 (cmos levels) sc 51 o memory shift clock output (cmos levels) dai15 52 i memory input data bit 15 (cmos levels) dao15 53 o memory output data bit 15 (cmos levels) dai14 54 i memory input data bit 14 (cmos levels) dao14 55 o memory output data bit 14 (cmos levels) dai13 56 i memory input data bit 13 (cmos levels) dao13 57 o memory output data bit 13 (cmos levels) dai12 58 i memory input data bit 12 (cmos levels) dao12 59 o memory output data bit 12 (cmos levels) dai11 60 i memory input data bit 11 (cmos levels) dao11 61 o memory output data bit 11 (cmos levels) v ddd(p3) 62 s digital supply voltage 3 for periphery (5.0 v); note 2 v ssd(p3) 63 s digital ground 3 for periphery; note 1 dai10 64 i memory input data bit 10 (cmos levels) dao10 65 o memory output data bit 10 (cmos levels) dai9 66 i memory input data bit 9 (cmos levels) dao9 67 o memory output data bit 9 (cmos levels) dai8 68 i memory input data bit 8 (cmos levels) dao8 69 o memory output data bit 8 (cmos levels) cas 70 o memory column address strobe output (cmos levels) ad0 71 o memory address output bit 0 (cmos levels) ad1 72 o memory address output bit 1 (cmos levels) ad2 73 o memory address output bit 2 (cmos levels) ad3 74 o memory address output bit 3 (cmos levels) v ssd(p4) 75 s digital ground 4 for periphery; note 1 v ddd(p4) 76 s digital supply voltage 4 for periphery (5.0 v); note 2 we 77 o memory write enable output (cmos levels) ras 78 o memory row address strobe output (cmos levels) ad8 79 o memory address output bit 8 (cmos levels) ad7 80 o memory address output bit 7 (cmos levels) ad6 81 o memory address output bit 6 (cmos levels) symbol pin i/o description
2000 jan 13 7 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs ad5 82 o memory address output bit 5 (cmos levels) ad4 83 o memory address output bit 4 (cmos levels) n.c. 84 - not used in application v ddd(c4) 85 s digital supply voltage 4 for core (3.3 v); note 3 v ssd(c4) 86 s digital ground 4 for core; note 4 v ssd(c5) 87 s digital ground 5 for core; note 4 v ddd(c5) 88 s digital supply voltage 5 for core (3.3 v); note 3 v ddd(p5) 89 s digital supply voltage 5 for periphery (5.0 v); note 2 v ssd(p5) 90 s digital ground 5 for periphery; note 1 v dda(sh) 91 s supply of sub hsync input (5.0 v) v ssa(sp) 92 s analog ground for sub channel pll v dda(sp) 93 s analog supply voltage for sub channel pll (3.3 v) shsync 94 i horizontal sync input for sub channel (cmos levels with hysteresis) svsync 95 i vertical sync input for sub channel (cmos levels with hysteresis) tsclk 96 i test clock input for sub (cmos levels) tsmsb 97 o test sub msb output for pll counter (cmos levels) tsext 98 i set sub pll input for external mode (cmos levels) v dda(sa) 99 s analog supply voltage for sub channel adcs (3.3 v) v ssa(sa) 100 s analog ground for sub channel adcs sv 101 i analog v input of sub channel v dda(sf) 102 s analog supply voltage for sub channel frontend (3.3 v) su 103 i analog u input of sub channel v bias(sa) 104 i/o analog bias reference input for sub channel adcs sy 105 i analog y* input of sub channel v ref(b)(sa) 106 i/o analog bottom reference for sub channel adcs v ref(t)(sa) 107 i/o analog top reference for sub channel adcs v ssd(c6) 108 s digital ground 6 for core; note 4 v ddd(c6) 109 s digital supply voltage 6 for core (3.3 v); note 3 tcbc 110 i test control block clock input (cmos levels) tcbd 111 i test control block data input (cmos levels) tcbr 112 i test control block reset input (cmos levels) v ddd(p) 113 s digital supply voltage for periphery (5.0 v); note 5 a0 114 i address select pin input (i 2 c-bus) (cmos levels) sda 115 i/o serial input data/ack output (i 2 c-bus) (cmos input levels) scl 116 i serial clock input (i 2 c-bus) (cmos levels) por 117 i power-on reset input (cmos levels with hysteresis and pull-up resistor to v dd ) tc 118 i test control input (cmos levels) tm1 119 i/o test mode input/output (cmos levels with hysteresis and pull-up resistor to v dd ) tm2 120 i/o test mode input/output (cmos levels with hysteresis and pull-up resistor to v dd ) tm0 121 i test mode input (cmos levels) v ddd(c7) 122 s digital supply voltage 7 for core (3.3 v); note 3 symbol pin i/o description
2000 jan 13 8 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs notes 1. all periphery v ss(p) are internally connected to each other, unless otherwise specified. 2. all periphery v dd(p) are internally connected to each other, unless otherwise specified. 3. all core v dd(c) are internally connected to each other. 4. all core v ss(c) are internally connected to each other. 5. this pin is not connected to the other periphery v dd(p) . v ssd(c7) 123 s digital ground 7 for core; note 4 v ref(t)(ma) 124 i/o analog top reference for main channel adcs v ref(b)(ma) 125 i/o analog bottom reference for main channel adcs my 126 i analog y* input for main channel v bias(ma) 127 i/o analog bias reference for main channel adcs mu 128 i analog u input for main channel symbol pin i/o description
2000 jan 13 9 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs fig.2 pin configuration. handbook, full pagewidth mgs387 SAB9079hs 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 101 102 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 sv v dda(sf) v ssa(sa) v dda(sa) tsext tsmsb tsclk svsync shsync v dda(sp) v ssa(sp) v dda(sh) v ssd(p5) v ddd(p5) v ddd(c5) v ssd(c5) v ssd(c4) v ddd(c4) n.c. ad4 ad5 ad6 ad7 ad8 v ddd(p4) v ssd(p4) ad3 ad2 ad1 ad0 dao8 dai8 dao9 dai9 dao10 mv v dda(mf) v ssa(ma) v dda(ma) tmext tmmsb tmclk mvsync mhsync v dda(mp) v ssa(mp) v dda(mh) v ssd(p1) v ddd(p1) v ddd(c1) v ssd(c1) v ssd(c2) v ddd(c2) dfb dhsync dvsync v ddd(c3) v ssd(c3) dy v ref(t)(da) v ref(b)(da) du v bias(da) dv v ssa(da) v dda(da) dai7 dai6 dai5 dai4 dai3 dai2 dai1 40 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 127 128 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 v bias(ma) mu my v ref(b)(ma) v ref(t)(ma) v ssd(c7) v ddd(c7) tm0 tm2 tm1 tc por scl sda a0 v ddd(p) tcbr tcbd tcbc v ddd(c6) v ssd(c6) v ref(t)(sa) v ref(b)(sa) sy v bias(sa) su dai0 dao0 dao1 dao2 dao3 dao4 dao5 v ssd(p2) v ddd(p2) dao6 dao7 sc dai15 dao15 dai14 dao14 dai13 dao13 dai12 dao12 dai11 dao11 v ddd(p3) v ssd(p3) dai10 dt cas we ras
2000 jan 13 10 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs system description pip modes an overview of the general pip modes is given in figs 3, 4 and 5. these pictures do not refer to all possible modes the device can handle. these modes are guaranteed only when sufficient memory is available and enough time is available to fetch all data from the memory. fig.3 pip modes. handbook, halfpage mgd594 sp-small handbook, halfpage mgd595 sp-medium handbook, halfpage mgd596 sp-large handbook, halfpage mgd597 dp handbook, halfpage mgd598 twin-pip handbook, halfpage mgd587 full field still full field live
2000 jan 13 11 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs fig.4 pip modes (continued). handbook, halfpage mgd589 pop-right handbook, halfpage mgd588 pop-left handbook, halfpage mgd590 pop-double handbook, halfpage mgs388 handbook, halfpage mgs389 handbook, halfpage mgs390
2000 jan 13 12 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs handbook, halfpage mgl925 mp13 fig.5 pip modes (continued). handbook, halfpage mgd591 mp7 handbook, halfpage mgd592 mp8 handbook, halfpage mgd584 quatro handbook, halfpage mgd585 mp9 handbook, halfpage mgd586 mp16
2000 jan 13 13 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs acquisition window the acquisition window is 720 pixels. this is related to a whole line of 896 pixels. so for pal will be acquired from the active video. for ntsc this will be slightly less . the vertical acquisition window is 228 lines for ntsc and 276 lines for pal. data will be acquired in a 4 :2:2 format. the acquisition clock is 896 hsync. acquisition ?ne positioning all i 2 c-bus settings relate to the incoming hsync, whether this is a real hsync or a burstkey for horizontal positioning. the same applys for the incoming vsync for vertical positioning. the relationships between the acquisition window and the internal clamp pulse are illustrated in fig.6. in an application the clamp pulse must be positioned, by the i 2 c-bus, between the hsync and the start of the active video of the incoming signal. display window the display window available for pip pictures is also 720 pixels wide, related to a 896 pixels line. the vertical display window is 228 lines for ntsc and 276 lines for pal. background window the origin of the display window is referenced to the origin of the background window. the background area is 768 pixels wide. vertically it is 238 lines for ntsc and 286 lines for pal. display ?ne positioning the i 2 c-bus defined fine positioning has relationships to the internal hsync and vsync as illustrated in fig.7. 720 896 --------- - 64 m s 720 896 --------- - 63.5 m s fig.6 acquisition fine positioning. handbook, full pagewidth mgs391 mahfp mavfp cidel ciper 228/276 lines 720 pixels the grey area depicts the background.
2000 jan 13 14 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs fig.7 display fine positioning. handbook, full pagewidth mgs392 bghfp bgvfp main channel sub channel sdhfp mdvfp mdhfp sdvfp 238/286 lines 768 pixels the grey area depicts the background. yuv to rgb conversion matrix a yuv to rgb conversion matrix is available. the nine matrix coefficient values can be set by i 2 c-bus commands. two sets can be defined; one for pal and one for ntsc. the matrix must be switched on, otherwise a 1 : 1 conversion takes place and y*, u and v will be unmodified. the conversion matrix is based on the following equations. all results (r, g and b) fall in the range from 0 to 1. any results outside of this range will be clipped to the nearest end value. it should be noted that gamma correction is not applied as is common practice. the end of this section contains an example. normalised y, u and v (indicated by subscript a) are given by the following four equations: 1. y a =x r a +y g a +z b a 2. x+y+z=1 3. u a =b a - y a 4. v a =r a - y a absolute or discrete (indicated by subscript d) values for y, u and v are given by the following three equations: 1. y d = 255 y a (v), y a normalised (range 0 to 1) 2. , u a normalised (range - 1 to +1) 3. , v a normalised (range - 1 to +1) u d 128 127 u a 1z C ----------- - + = v d 128 127 v a 1x C ----------- - + =
2000 jan 13 15 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs absolute or discrete (indicated by subscript d) values for r, g and b are given by the following three equations: 1. 2. 3. the implementation of a matrix with 9 coefficients is shown in table 1. table 1 matrix coef?cients so, for example; r=ry y d +ru 2 (u d - 128) + rv 2 (v d - 128) table 2 shows how the coefficients can be calculated for a specific case where x = 0.299, y = 0.587 and z = 0.114. calculation of xv:y* 128 (rounded to the nearest integer), translates to a binary value. calculation of xu:xv: translates to a binary value with the coefficients for the binary bits: - 1, 1 2 1 4 , 1 8 , 1 16 , 1 32 , 1 64 1 128 (lsb). table 2 coef?cient calculation yuv to rgb matrix coefficients y d u d v d cofactor: y d cofactor: 2 (u d - 128) cofactor: 2 (v d - 128) r ry=1 ru=0 ggy=1 b by=1 bv=0 coefficient expression decimal value binary value ry 1 1 10000000 ru 0 0 00000000 rv 0.704 01011010 gy 1 1 10000000 gu - 0.173 11101010 gv - 0.358 11010010 by 1 1 10000000 bu 0.889 01110010 bv 0 0 00000000 r d y d 255 127 --------- - v d 128 C () 1x C () + = g d y d 255 127 --------- - x y -- - ? ?? 1x C () v d 128 C () C 255 127 --------- - z y -- - ? ?? 1z C () u d 128 C () C = b d y d 255 127 --------- - u d 128 C () 1z C () + = rv 255 254 --------- - 1x C () = gu 255 254 --------- - z y -- - 1z C () C = gv 255 254 --------- - x y -- - 1x C () C = bu 255 254 --------- - 1z C () = 255 254 --------- - 1x C () 255 254 --------- - z y -- - 1z C () C 255 254 --------- - x y -- - 1x C () C 255 254 --------- - 1z C ()
2000 jan 13 16 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs pll phase shift compensation for vcr when a vcr is applied as source for the main channel, a large phase jump can appear when the vcr head switches to another field. since this phenomenon occurs around the vsync, its effects can be compensated. a prediction mechanism generates a compensation window around the vsync. this window can be manipulated with two parameters; vspre and vspost. vspre sets the number of lines before the predicted vsync, where the compensation window will start vspost sets the number of lines after the actual vsync, where the compensation window will end. i 2 c-bus i 2 c- bus control the SAB9079hs is a slave receiver/transmitter. the protocols are given in tables 3 and 5. table 3 i 2 c-bus slave receiver protocol table 4 description of table 3 table 5 i 2 c-bus slave transmitter protocol table 6 description of table 5 s slave a sub a data a data a p symbol description s start condition a acknowledge bit (generated by SAB9079hs) p stop condition slave slave address; the data transmission starts with the slave address byte slv (2ch or 2eh); the lsb of the slv byte is the r/ w bit which is logic 0 in slave receiver mode sub sub address byte; the sub byte indicates the sub address which has to be written; if more than one data byte is send (as above) the internal sub address counter is automatically incremented after each data byte data data byte; the data byte is the actual data written to the sub address; the functions of each sub address are explained in the following sections sslaveadataadataadatan p symbol description s start condition a acknowledge bit; after the slv generated by the SAB9079hs; after the data generated by the master n acknowledge not bit; given by the master after the last data byte p stop condition slave slave address; the data transmission starts with the slave address byte slv (2dh or 2fh); the lsb of the slv byte is the r/ w bit which is logic 1 in slave transmitter mode data data byte; this is put on the bus by SAB9079hs in an auto increment mode; if the master gives an acknowledge the next data byte is sent; if the SAB9079hs has sent all its data it starts again with the ?rst data byte and the sequence is repeated; this continues until an acknowledge not is given by the master
2000 jan 13 17 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs the SAB9079hs has 8 read/status registers. the last 7 registers are reserved for future purposes. reading a reserved register will return zero values. the SAB9079hs has 192 write registers. writing to a reserved register is not allowed. an overview of all write registers is given in table 7. table 7 description of write registers i 2 c- bus read registers the SAB9079hs has 8 read/status registers. the register currently used are listed in table 8. the remaining 7 are reserved for future purposes. reading a reserved register will return zero values. table 8 i 2 c-bus read registers sub address range purpose 00h to 04h display 05h to 11h positioning and sizing of pips 12h to 17h decoder settings 18h to 1fh acquisition control 20h to 25h decoder and pll settings 26h to 28h reserved 29h to 2ah decoder and pll settings 2bh to 2fh replay settings 30h to 37h border and colour settings 38h to 3ch osd controls 3dh to 4eh yuv to rgb conversion matrix settings 4fh to 5fh extra decoder settings 60h to 7fh reserved 80h to dfh osd characters e0h to ffh reserved sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h snonint mask id repchano 01h reserved 02h reserved 03h reserved 04h reserved 05h reserved 06h reserved 07h reserved
2000 jan 13 18 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs snonint this bit indicates the internal interface status of the sub channel. a logic 0 indicates that the channel is in interlaced mode, a logic 1 indicates that the channel is non-interlaced. mask id this bit gives the version number of the chip. a logic 0 indicates that a SAB9079n1 is used, a logic 1 indicates that a SAB9079n2 is used. repchano these bits indicate the present picture number, counting from 0, where replay acquisition is writing. i 2 c- bus display setting registers mpipon and spipon if mpipon is set to logic 1 (see table 10) the main pip is on. if it is set to logic 0 the main pip is off. if spipon is set to logic 1 the sub pips are on, in accordance with the scheme of the pipg bits (see section positioning and sizing of pips). if spipon is set to logic 0 all the sub pips are off. this can also be achieved by setting all pipg bits to zero. mfreeze and sfreeze mfreeze and sfreeze control the writing of data to the vdram. if set to logic 0 the writing to the vdram is disabled after the next vsync. if set to logic 1 the writing is enabled after the next vsync. i 2 chold the i 2 c-bus hold bit is set to logic 0 (default). this means that all i 2 c-bus data is directly clocked into the internal registers. a part of the i 2 c-bus data will be clocked in on the next vsync (e.g. the reduction factors and the display positioning). if the i 2 chold bit is logic 1 that part of the i 2 c-bus will not be clocked in on the next vsync. to make the data available the i 2 chold bit should be set to logic 0 again. this function is useful when much data has to be sent and a screen update is not allowed when sending this data. a list of i 2 c-bus registers which are clocked in on a vsync is given below: mpipon and spipon mfreeze, sfreeze and fillset dnonint, mnonint and snonint prio bghfp, bgvfp, mdhfp, mdvfp, sdhfp and sdvfp mhpic, mvpic, shpic, svpic, shdis and svdis pipg c,r mhred, mvred, shred, svred, mlsel, slsel and sbsel osdhfp, osdvfp, osdhdis and osdvdis. fillset and filloff the fillset bit sets the colour of all sub pips immediately to a 30% grey value if is set to logic 1. if fillset is set to logic 0 then the 30% grey pips stay until the data in the vdram is updated (unfrozen). this bit should be used in the event that a new pip mode is made in which the vdram data becomes invalid. filloff works the opposite to fillset. if this bit is set all the vdram data is made visible in the pips and no pip has a grey content. this bit is generally not used. mis if the mis bit is set to logic 0 the main and sub channels have their own independent memory spaces. if set to logic 1 the main and sub channels share the same memory space, this is only valid if the main and sub channels have the same reduction factors. yuvfilter these bits control the vertical filtering of 1 : 1 for both the y* and uv channels independently. several display filter modes can be set with these bits. an overview is given in table 9. the y filter should not be used in vertical 1 1 modes. table 9 display ?lter modes cte and lte colour transient enhancement (cte) can be set on or off. luminance transient enhancement (lte) is controllable via a scale, setting the scale value to 0h means that lte is off. mode yuv filter no ?lter 00h uv 1 : 1 vertical ?lter 01h y1:1 ver tical ?lter 10h yuv1:1 ver tical ?lter 11h
2000 jan 13 19 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs mfld and sfld the number of ?elds stored in the vdram can be set with the mfld and sfld bits. there is a limit of 4 mbits which can be stored. it is best to set these bits so that 3 ?elds are stored for the sub channel and 2 for the main channel, but this is not possible in all cases (large pips). therefore, the number of ?elds stored can be reduced. this can result in some performance loss, e.g. if the sub channel is set to 1 ?eld joint line errors can appear. intoff, dnonint, mnonint and snonint in automatic interlace mode (intoff is logic 0) the device calculates whether interlaced or non-interlaced signals are applied and acts accordingly. this can be overruled by setting bit intoff to logic 1. bits dnonint, mnonint and snonint then determine the interlace. if the xnonint bits are set to logic 0 the device is put in interlaced mode, if they are set to logic 1 the main, sub and/or display channels are put in non-interlaced mode. dnonint overrules mnonint (main and display channels are coupled). paloff, dpal, mpal and spal in automatic mode (paloff is logic 0) the device calculates what type of signal is applied, pal or ntsc. in the event that the number of lines in a field is less than 287 it is assumed to be ntsc, otherwise it is assumed to be pal. this can be overruled by setting paloff to logic 1. the xpal bits then determine the mode of the device. a logic 0 sets the device in ntsc mode, a logic 1 to pal mode. dpal overrules mpal (main and display channels are coupled). prio, nipcoff, fmt411, dfilt and yth the prio bit sets the priority between the main and sub channels. a logic 0 gives priority to the sub channel which means that the sub channel pips, if present, are placed on top of the main pip. a logic 1 places the main pip on top of the sub pips. the nipcoff bit determines whether a grey bar is inserted in case a ntsc pip is displayed in a pip with pal pip size. the missing lines are equally divided between the top part and the bottom part of the pip window and made 30% grey. if this bit is logic 0 the grey bar is displayed, if this bit is logic 1 the grey bar is omitted and the pip data is shifted up. the fmt411 bit sets the yuv format. if this bit is logic 0 then the device is in 4:2:2yuv mode, if this bit is logic 1 then the device is in 4:1:1 yuv mode. if the 4:2:2 format is used the memory use is larger, so some modes are not available and the length of a read/write cycle is larger. the dfilt bit controls an interpolating filter to expand the internal 720 pixels data rate to the output data rate of 2 720 pixels in 1fh mode. if dfilt is logic 1 then the filter is on. the yth (3 : 0) bits control the video output. if the current y value is less then yth 16 then the fast blanking is switched off, and the original live background will be visible. this feature can be used to pick up sub-titles and display them as osd anywhere on the screen. table 10 overview of the i 2 c-bus sub addresses sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h mpipon spipon mfreeze sfreeze i 2 chold fillset filloff mis 01h ---- mfld (1 : 0) sfld (1 : 0) 02h yuvfilter (1 : 0) -- cte lte (2 : 0) 03h intoff dnonint mnonint snonint paloff dpal mpal spal 04h prio nipcoff fmt411 dfilt yth (3 : 0)
2000 jan 13 20 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs p ositioning and sizing of pip s the basic principle is the same as in the sab9076/77. the only difference is that the main channel can only display 1 pip. the algorithm for the sub channel is similar. the difference for the sub channel is that the number of pips for each row and the offset of the first pip is replaced by grid bits. in the matrix of 16 pips every pip can be put on or off. the i 2 c-bus registers are given in table 11. bghfp and bgvfp the bghfp and bgvfp bits control the horizontal (4 pixels/step) and vertical (2 line/field/step) background positioning (upper left corner). sdhfp and sdvfp the sdhfp and sdvfp bits control the horizontal (4 pixels/step) and vertical (1 line/field/step) sub display positioning (upper left corner). shpic and svpic bit shpic controls the horizontal size of the sub pip in steps of 4 pixels (minimum is 8 pixels). bit svpic controls the vertical size of the sub pip in steps of 1 line/field for ntsc or 2 lines/field for pal. shdis and svdis bit shdis controls the horizontal distance between the left sides of the sub pips on a row in steps of 4 pixels. bit svdis controls the vertical distance between the top lines of sub pips in steps of 1 line (both pal and ntsc). the distances should always be equal or larger than the picture sizes so that the pips of one channel do not overlap. in the event of single pip modes shdis should be set to maximum. mdhfp and mdvfp the mdhfp and mdvfp bits control the horizontal and vertical main display positioning. mhpic and mvpic bit mhpic controls the horizontal size of the main pip in steps of 4 pixels (minimum is 24 pixels). bit mvpic controls the vertical size of the main pip in steps of 1 line/field for ntsc or 2 lines/field for pal. pipg row,col the pipg row,col bits make it possible to set each individual pip on or off in a multi pip mode. pips are numbered according to table 12. rows are numbered from top to bottom, columns are numbered from left to right. table 11 i 2 c-bus registers for pip sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05h bghfp (3 : 0) bgvfp (3 : 0) 06h sdhfp (7 : 0) 07h sdvfp (7 : 0) 08h shpic (7 : 0) 09h svpic (7 : 0) 0ah shdis (7 : 0) 0bh svdis (7 : 0) 0ch mdhfp (7 : 0) 0dh mdvfp (7 : 0) 0eh mhpic (7 : 0) 0fh mvpic (7 : 0) 10h pipg 1,3 pipg 1,2 pipg 1,1 pipg 1,0 pipg 0,3 pipg 0,2 pipg 0,1 pipg 0,0 11h pipg 3,3 pipg 3,2 pipg 3,1 pipg 3,0 pipg 2,3 pipg 2,2 pipg 2,1 pipg 2,0
2000 jan 13 21 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs table 12 pip numbering row column 0 column 1 column 2 column 3 0 pipg 0,0 pipg 0,1 pipg 0,2 pipg 0,3 1 pipg 1,0 pipg 1,1 pipg 1,2 pipg 1,3 2 pipg 2,0 pipg 2,1 pipg 2,2 pipg 2,3 3 pipg 3,0 pipg 3,1 pipg 3,2 pipg 3,3 a cquisition control acquisition control sets the reduction factors, the acquisition fine positioning and the channel selection bits are given in table 13. shred, svred, mhred and mvred the reduction factors can be set in accordance with table 14. sahfp and savfp the sahfp and savfp bits control the horizontal (2 pixels/step) and vertical (1 line/field/step) sub acquisition positioning (upper left corner). when sahfp is set to logic 0, the sub channel will enter the freeze mode. mahfp and mavfp the mahfp and mavfp bits control the horizontal (2 pixels/step) and vertical (1 line/field/step) main acquisition positioning (upper left corner). when mahfp is set to logic 0, the main channel will enter the freeze mode. slsel and mlsel bits slsel and mlsel select which pip is updated. a maximum of 16 pips can be displayed for the sub channel. the number counting is done from the left to right and from top to bottom. if all pips are on (see table 12) 16 pips are displayed. if pips are put off the maximum number is limited to the number of pips displayed. in the pip mode where the main and sub channel have the same reduction factors the main channel can write in sub vdram address spaces according to the same numbering. in all other cases mlsel is inoperative and should be set to 0h. for replay and other trick modes more pips can be stored and addressed via the higher numbers (17 to 60). the numbers 61, 62 and 63 are not valid. table 13 acquisition and channel selection bits sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 18h - svred (2 : 0) - shred (2 : 0) 19h - mvred (2 : 0) - mhred (2 : 0) 1ah sahfp (7 : 0) 1bh savfp (7 : 0) 1ch mahfp (7 : 0) 1dh mavfp (7 : 0) 1eh -- slsel (5 : 0) 1fh -- mlsel (5 : 0)
2000 jan 13 22 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs table 14 reduction factors bits horizontal vertical main sub main sub 0h not valid not valid not valid not valid 1h 1 1 1 1 1 1 1 1 2h 1 2 1 2 1 2 1 2 3h 1 3 1 3 1 3 1 3 4h 1 4 1 4 1 4 1 4 5h 2 3 not valid not valid not valid 6h 1 6 1 6 not valid not valid 7h 3 4 not valid not valid not valid d ecoder and pll settings syclref, suclref, svclref, myclref, muclref and mvclref the clamp reference level can be set separately for each of the 6 analog inputs; it acts as a wide range pedestal. under normal conditions syclref will be set to 0 and suvclref will be set to 128. dhsel, fidon, vfilt, uvpol, vspol, fpol and ccon dhsel determines the timing of the hsync pulse (burstkey = 0 or hsync = 1), for the display part fidon enables the field identification position fine tuning; fidon = 1 takes the value of registers 4fh or 57h; fidon = 0 takes a hard wired default value vfilt enhances the vertical reduction filter for vertical reduction modes 1 3 and 1 4 suvpol and muvpol invert the uv polarity of the yuv data duvpol inverts the uv polarity of the border colours vspol determines the active edge of the vsync (positive edge is logic 0 and negative edge is logic 1) fpol can invert the field id of the incoming fields ccon enables the clamp correction circuit. intcoff, fbdel and ydel bit intcoff sets the interlace correction. interlace correction is put off if this bit is set to logic 1. fbdel (2 : 0) can adjust the fast blank delay in 8 steps of a 1 2 28 mhz clock cycle ( - 4 to +3); 0h is mid-scale. ydel adjusts the y delay with respect to the uv delay; 0h is mid-scale from - 4to+3 pixels. ydel is done on the display side and therefore both channels, main and sub channels, will have an equal delay in the luminance. pedestals on the acquisition sides yuv can be given an offset during the clamp. using this mechanism minor offsets in the matrices can be adjusted. the steps are from - 8 to +7 with a resolution of 1 lsb of the adc. vspre and vspost vspre is the number of lines before a vsync where the pll is put in free-running mode. vspost is the number of lines after the vsync where the pll is still free-running. outside this area the pll is in normal mode.
2000 jan 13 23 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs table 15 decoder and pll settings sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12h syclref (7 : 0) 13h suclref (7 : 0) 14h svclref (7 : 0) 15h myclref (7 : 0) 16h muclref (7 : 0) 17h mvclref (7 : 0) 20h -- sfidon svfilt suvpol svspol sfpol sccon 21h dhsel - mfidon mvfilt muvpol mvspol mfpol mccon 22h intcoff fbdel (2 : 0) duvpol ydel (2 : 0) 23h spedesty (3 : 0) mpedesty (3 : 0) 24h spedestu (3 : 0) mpedestu (3 : 0) 25h spedestv (3 : 0) mpedestv (3 : 0) 29h -- vspre 2ah -- vspost r eplay settings dchaoff dchaoff is the channel offset for the display. it can be used in trick modes or software replay as the channel number to be displayed. dchadis dchadis is the number of internal vsyncs between two stored and/or displayed fields. repmax repmax is the maximum number of different fields that will be stored in the memory during replay. repinc repinc is the auto increment used during replay acquisition/display. repacq, repdisp, repcont, dcha+ and dcha - bit repacq enables the replay acquisition loop, in which pictures are stored with dchadis as time distance. bit repdisp enables the display of stored pictures. when bit repcont = 1 it enables a continuous looping during display, when bit repcont = 0 it enables the step function. bit dcha+ enables one step forward (next picture), bit dcha - enables one step back in time (previous picture). it should be noted that if bits repacq and repdisp are both logic 1 at the same time, the internal display number will be the present acquisition number minus 1.
2000 jan 13 24 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs table 16 replay settings note 1. rgbon enables the yuv to rgb matrix. it is not related to the replay registers. sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2bh -- dchaoff (5 : 0) 2ch dchadis (7 : 0) 2dh -- repmax (5 : 0) 2eh dcha+ dcha - repacq repdisp repcont -- rgbon (1) 2fh -- repinc (5 : 0) b order and colour settings several border and colour settings are given in table 17. bhsize and bvsize bits bhsize and bvsize control the horizontal and vertical border size in steps of 2 pixels and 1 line. ouvpol bit ouvpol sets the uv polarity for all the osd related colours. fblon if bit fblon is set to logic 1 the fbl pin is made high under the condition that standard signals are applied. if pal signals are applied, this function is overruled for the sab9078hs. shade bit shade gives the osd characters a shade. osdblk bit osdblk blanks all osd characters but retains their values in memory. colour registers the colour registers are all built-up in a similar way: bit 6 is the on bit which determines whether the border (or osd) is visible bits 5 and 4 determine the brightness level of the colour (see table 18) bits 2, 1 and 0 determine the colour type (see table 18) sb = sub border sbs = sub border select (which pip has a different border colour) mb = main border bg = back ground osd is the osd character osds = the background of the selected osd character. sbsel the sbsel bits select which sub pip has a different border colour, if sbson is set to logic 1. the colour type can be set with sbsbrt and sbscol.
2000 jan 13 25 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs table 17 border and colour settings table 18 colour registers sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 30h bhsize (3 : 0) bvsize (3 : 0) 31h - sbon sbbrt (1 : 0) - sbcol (2 : 0) 32h - sbson sbsbrt (1 : 0) - sbscol (2 : 0) 33h - mbon mbbrt (1 : 0) - mbcol (2 : 0) 34h fblon bgon bgbrt (1 : 0) - bgcol (2 : 0) 35h ouvpol osdon osdbrt (1 : 0) - osdcol (2 : 0) 36h shade osdblk osdsbrt (1 : 0) - osdscol (2 : 0) 37h ---- sbsel (3 : 0) colour type brightness levels colour value 0h 1h 2h 3h white (low) 0h 0% 10% 30% 50% blue 1h 30% 50% 70% 100% red 2h 30% 50% 70% 100% magenta 3h 30% 50% 70% 100% green 4h 30% 50% 70% 100% cyan 5h 30% 50% 70% 100% yellow 6h 30% 50% 70% 100% white (high) 7h 60% 70% 80% 100% osd controls osd can be placed on the screen in 4 rows of 4 strings. each string can hold up to 6 characters. they can be placed on top of the sub pips. fine positioning is done with the osdhfp and osdvfp bits. the osdhdis bits determine the distance between the strings and osdvdis determine the distance between the rows (see table 19). osdhfp and osdvfp bits osdhfp and osdvfp control the fine positioning of the osd text in steps of 4 pixels and 1 line. osdhdis and osdvdis bit osdhdis determines the distance between the strings (in steps of 4 pixels) and bit osdvdis determines the distance between the rows (in steps of 1 line). osdexp it is possible to expand the osd characters. 0xh is standard, 10h doubles the size and 11h quadruples the size. osdbg and osdtr bit osdbg sets the osd background. bit osdtr sets the transparency of the osd background; the options are given in table 20. osdhrep and osdvrep bit osdhrep (see table 21) sets the actual number of strings per row (a maximum of 4). bit osdvrep sets the actual number of rows (a maximum of 4).
2000 jan 13 26 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs table 19 osd control registers table 20 osd background table 21 row and string settings osd characters the osd characters can be written to i 2 c-bus sub address 80h and higher (see table 22). the index osdchr pos,row,col indicates the character position in the string, the row number and the column number of the string. table 22 osd write register sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 38h osdhfp (7 : 0) 39h osdvfp (7 : 0) 3ah osdhdis (7 : 0) 3bh osdvdis (7 : 0) 3ch osdexp osdbg osdtr osdhrep (1 : 0) osdvrep (1 : 0) mode osdbg osdtr note only osd 0 x pip (bg) osd with bg 1 0 30% white transparent 1 1 50% pip/30% white osdxrep value osdhrep nr. of strings osdvrep nr. of rows 00b 1 1 01b 2 2 10b 3 3 11b 4 4 sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 80h osdchr 0,0,0 81h osdchr 0,0,1 82h osdchr 0,0,2 83h osdchr 0,0,3 84h osdchr 0,1,0 85h osdchr 0,1,1 86h osdchr 0,1,2 86h osdchr 0,1,3 || deh osdchr 5,3,2 dfh osdchr 5,3,3
2000 jan 13 27 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs osdchr the osdchr byte is divided into groups. the lower 7 bits osdchr (6 : 0) contain the character to be displayed according to the character rom table. bit 7 indicates whether the character is selected, e.g. to change the background of that character. selecting the first character of a string selects the whole string; selecting any other character has no effect. table 23 character rom table; see also fig.8 note 1. rows 0h and 1h are not completely represented because of their graphical contents (e.g. a smiley). upper 3 bits lower 4 bits 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh 0h 1h 3 4 2 3 1 6 1 4 1 3 1 2 1 1 2h !#$%&()*+,-./ 3h 0123456789 : ; <=>? 4h @abcdefgh i j klmno 5h pqr s t u vwx y z [ \ ] ^ _ 6h `abcde f gh i j k lmno 7h pqrstuvwxyz{ | }~
2000 jan 13 28 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs mgs828 handbook, full pagewidth upper 3 bits 0h 1h 2h 3h 4h 5h 6h 7h lower 4 bits 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h ah bh ch dh eh fh fig.8 osd character set.
2000 jan 13 29 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs yuv to rgb conversion matrix settings rgbon rgbon enables the yuv to rgb matrix. xxcoefn (all coef?cients) the yuv to rgb conversion matrix has the following 3 equations: 1. r = rycoef y d + rucoef 2 (u d - 128) + rvcoef 2 (v d - 128) 2. g = gycoef y d + gucoef 2 (u d - 128) + gvcoef 2 (v d - 128) 3. b = bycoef y d + bucoef 2 (u d - 128) + bvcoef 2 (v d - 128) in this equation y d is normalised for the range 0 to 255, u d and v d for the range - 128 to 128. the uv coefficients are twos complement in the range - 1 coef < 1. the y coefficients are positives in the range 0 coef < 2. for pal pictures the coef1 values are used, for ntsc the coef2 values. table 24 conversion settings note 1. dcha+, dcha - , repacq, repdisp and repcont are used for replay settings. they are not related to the conversion matrix. sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2eh dcha+ dcha - repacq repdisp repcont -- rgbon 3dh rycoef1 (7 : 0) 3eh rucoef1 (7 : 0) 3fh rvcoef1 (7 : 0) 40h gycoef1 (7 : 0) 41h gucoef1 (7 : 0) 42h gvcoef1 (7 : 0) 43h bycoef1 (7 : 0) 44h bucoef1 (7 : 0) 45h bvcoef1 (7 : 0) 46h rycoef2 (7 : 0) 47h rucoef2 (7 : 0) 48h rvcoef2 (7 : 0) 49h gycoef2 (7 : 0) 4ah gucoef2 (7 : 0) 4bh gvcoef2 (7 : 0) 4ch bycoef2 (7 : 0) 4dh bucoef2 (7 : 0) 4eh bvcoef2 (7 : 0)
2000 jan 13 30 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs e xtra decoder settings cldel and clper xxcldel sets the delay from the rising edge of the hsync/burstkey to the beginning of the internally generated clamp pulse for signal xx in steps of 1 pixel. xxclper sets the pulse width of the internally generated clamp pulse in steps of 1 pixel. fidpos bit fidpos defines the position of the field identification window. the purpose is to set it so that the incoming vsync is halfway up the window. this allows a spread of 1 4 line for the vsync (vcr and/or less sophisticated decoder types) in steps of 2 pixels. vgate xvgate disables the detection of a next vsync for a number of lines, after detecting an initial one in steps of 1 line. smlpal if this bit is set to logic 1, the vertical acquisition and display window for pal is decreased from 276 lines to 258 lines tgact1, tgact2, tcolbar, tgeny, tgenu and tgenv for test purposes, a built-in colour bar/ramp generator is available which replaces the adc digital output data. this test generator is enabled if tgact1 and tgact2 are both set to logic 1, and is disabled when tgact2 is set to logic 0 (it is recommended to set tgact1 to logic 1). the test pattern (common for main and sub channels) is set to colour bar if tcolbar is set to logic 1 and set to a ramp if tcolbar is set to logic 0. both patterns start at a hsync pulse. by use of bit(s) tgenx (active logic 1) the y, u and v of the pattern can be controlled independently. table 25 extra decoder settings sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 4fh sycldel (7 : 0) 50h sucldel (7 : 0) 51h svcldel (7 : 0) 52h -- syclper (5 : 0) 53h -- suclper (5 : 0) 54h -- svclper (5 : 0) 55h sfidpos (7 : 0) 56h -- svgate (5 : 0) 57h mycldel (7 : 0) 58h mucldel (7 : 0) 59h mvcldel (7 : 0) 5ah -- myclper (5 : 0) 5bh -- muclper (5 : 0) 5ch -- mvclper (5 : 0) 5dh mfidpos (7 : 0) 5eh -- mvgate (5 : 0) 5fh smlpal - tgact1 tgact2 tcolbar tgeny tgenu tgenv
2000 jan 13 31 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs dacs these are 8-bit dacs. the maximum output sample frequency is 28 mhz. acquisition channel adcs and clamping the analog input signals are converted to digital signals by means of three adcs. the resolution of the adcs is 8-bit (dnl is 7-bit, inl is 6-bit) and the sampling is done at the system frequency of 14 mhz. the inputs should be ac-coupled and an internal clamp circuit will clamp the input to v ref(b)(sa/ma) for the luminance channels and to for the chrominance channels. the clamping starts at the active edge of the internally generated clamp period signal. the clamp period signal, generated from the hsync pulse, has a delay adjusted with the xxcicel bits with respect to the hsync. internal video buffers amplify the standard input signals y*, u and v to the correct adc levels. the bandwidth of the input signals should be limited to 4.5 mhz for the y input and 1.125 mhz for the u and v inputs. pll the pll generates, from the hsync, an internal system clock of 3584 hsync which is approximately 56 mhz. the other system clocks are derived from this clock. they are in the range 3584, 1792, 896 or 448 hsync. v ref(t)(sa/ma) v ref(b)(sa/ma) + 2 ---------------------------------------------------------------------- - lsb 2 ---------- - + limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model; see uzw-b0/fq-b302 . 2. machine model; see uzw-b0/fq-a302 . quality specification according to snw-fq-611 part e , dated 14 december 1992. the numbers of the quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9397 750 00192. thermal characteristics symbol parameter conditions min. max. unit v ddd(p) digital supply voltage for the peripheral - 0.5 +6.0 v v ddd(c) digital supply voltage for the core - 0.5 +4.0 v v dda analog supply voltage - 0.5 +4.0 v p max maximum power dissipation - 1.5 w t stg storage temperature - 25 +150 c t amb ambient temperature 0 70 c v esd electrostatic handling note 1 - 3000 v note 2 - 300 v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 37 k/w
2000 jan 13 32 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs analog characteristics v ddd(p) = 5.0 v; v ddd(c) = 3.3 v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. type max. unit supplies v ddd(p)n all digital supply voltages for the peripheral 4.5 5.0 5.5 v v ddd(c)n all digital supply voltages for the core 3.0 3.3 3.6 v v dda analog supply voltages 3.0 3.3 3.6 v v ss(n) all ground voltages - 0 - v d v dd(max) maximum difference between supply voltages - 0 100 mv d v ss(max) maximum difference between ground voltages - 0 100 mv i ddd(q) quiescent current of digital supply voltages note 1 - 050 m a i vdda(mp) main pll analog supply current - 0.4 - ma i vdda(sp) sub pll analog supply current - 0.4 - ma i vdda(ma) main adcs supply current note 2 - 78 96 ma i vdda(sa) sub adcs supply current note 2 - 78 96 ma i vdda(da) dacs supply current note 3 - 10 17 ma i dda(tot) total analog supply current - 170 210 ma i ddd(tot) total digital supply current - 115 - ma analog-to-digital converter and clamping v vref(t)(sa/ma) top reference voltage note 4 2.65 2.82 2.95 v v vref(b)(sa/ma) bottom reference voltage note 4 0.95 1.08 1.20 v v iy(p-p) input signal amplitude (peak-to-peak value) note 5 - 1.00 1.04 v v iv(p-p) input signal amplitude (peak-to-peak value) note 5 - 1.05 1.10 v v iu(p-p) input signal amplitude (peak-to-peak value) note 5 - 1.33 1.38 v i i input current clamping off - 0.1 -m a clamping on; note 2 - 55 -m a c i input capacitance - 5 - pf f s sample frequency note 6 - 896xhsync - khz res resolution note 2 8 8 8 bit dnl differential non-linearity note 2 - 1.4 - +1.4 lsb inl integral non-linearity note 2 - 2.0 - +2.0 lsb a cs channel separation - 48 - db psrr power supply rejection ratio - 48 - db
2000 jan 13 33 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs notes 1. digital clocks are silent, por connected to v dd . 2. load resistance of v bias(ma) /v bias(sa) is 39 k w . 3. the load resistance of dac outputs is 1 k w . 4. the v vref(t)(sa/ma) and v vref(b)(sa/ma) are made by a resistor division of v dda . they can be calculated with the formulae: a) b) 5. the input signal is amplified to meet an internal peak-to-peak voltage level of v vref(t)(sa/ma) - v vref(b)(sa/ma) . 6. the internal system frequencies are 3584, 1792, 896 and 448 times the hsync input frequency. 7. the y* channel is clamped to the v vref(b)(sa/ma) of the adcs, which is derived from pin v ref(b)(sa) and pin v ref(b)(ma) . 8. the uv channels are clamped to 0.5 (v vref(t)(sa/ma) +v vref(b)(sa/ma) +v lsb ). where v lsb is one step of the adc. v clamp(y) clamping voltage level y note 7 1.25 1.35 1.45 v v clamp(uv) clamping voltage level uv note 8 1.80 1.95 2.10 v digital-to-analog converter and output stage v vref(t)(da) top reference voltage 1.10 1.20 1.30 v v vref(b)(da) bottom reference voltage 0.15 0.22 0.30 v r l load resistance 1 - 1000 k w c l load capacitance 0 - 50 pf f s sample frequency 1fh; note 6 - 1792hsync - khz 2fh; note 6 - 896hsync - khz res resolution 8 8 8 bit dnl differential non-linearity note 3 - 1.0 - +1.0 lsb inl integral non-linearity note 3 - 1.0 - +1.0 lsb a cs channel separation note 3 - 48 - db psrr power supply rejection ratio note 3 - 48 - db main pll and clock generation f i(pll)(main) input frequency 1fh note 6 14 15.75 18 khz sub pll and clock generation f i(pll)(sub) input frequency note 6 14 15.75 18 khz symbol parameter conditions min. type max. unit v vref(t)(sa/ma) v dda 2v ref(t)(nom) v dda(nom) ------------------------------ v = v vref(b)(sa/ma) v dda v ref(b)(nom) v dda(nom) -------------------------- - v =
2000 jan 13 34 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs colour path characteristics note 1. mismatch = (max - min)/average. symbol parameter conditions min. typ. max. unit g (conv)(my) analog y* input adc conversion gain for main channel 0.20 0.22 0.24 lsb/mv g (conv)(sy) analog y* input adc conversion gain for sub channel 0.20 0.22 0.24 lsb/mv g (conv)(mu) analog u input adc conversion gain for main channel 0.15 0.17 0.19 lsb/mv g (conv)(su) analog u input adc conversion gain for sub channel 0.15 0.17 0.19 lsb/mv g (conv)(mv) analog v input adc conversion gain for main channel 0.19 0.21 0.23 lsb/mv g (conv)(sv) analog v input adc conversion gain for sub channel 0.19 0.21 0.23 lsb/mv g (conv)(dy) analog y output adc conversion gain 6.0 6.8 7.5 lsb/mv g (conv)(du) analog u output adc conversion gain 6.0 6.8 7.5 lsb/mv g (conv)(dv) analog v output adc conversion gain 6.0 6.8 7.5 lsb/mv mm adc(y) analog y adc mismatch note 1 - 05% mm adc(u) analog u adc mismatch note 1 - 05% mm adc(v) analog v adc mismatch note 1 - 05% mm adc(yuv) analog yuv adc mismatch note 1 - 05%
2000 jan 13 35 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs digital characteristics all v ddd(c) pins = 3.0 to 3.6 v; t amb =0to70 c; unless otherwise speci?ed. note 1. the internal system frequencies are 3584, 1792, 896 and 448 times the hsync input frequency. test and application information tv application with insertion before 100 hz feature box (double window) in the 100 hz application the deflection circuit operates at 100 hz. the pip data is inserted into the main decoder output stream and fed to the feature box. the double window feature is made at 1fh and the field rate is doubled in the feature box. the internal synchronization is illustrated in fig.9. symbol parameter conditions min. type max. unit dc characteristics v ih high-level input voltage 70 -- %v ddd v il low-level input voltage -- 30 %v ddd v hys hysteresis voltage - 30 - %v ddd v oh high-level output voltage v ddd(p) - 0.4 -- v v ol low-level output voltage -- 0.4 v ? i li ? input leakage current v ddd = 3.6 v - 0.1 1 m a ? i oz ? 3-state input leakage current v ddd = 3.6 v - 0.2 1 m a r pu internal pull-up resistor 23 50 80 k w ac characteristics f sys system frequency note 1 - 3584xhsync khz t r rise time - 625ns t f fall time - 625ns handbook, full pagewidth mgs829 y*uv main and display sub decoder hv decoder switch y*uv feature box hv y*uv hv hv y*uv/rgb fbl fig.9 1fh/1fv application with insertion before the feature box.
2000 jan 13 36 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs s lave 2f h general description in the slave mode the main and display channel has to follow an external 2fh, xfv signal. the main acquisition cannot handle such a source, the main/display pll can. thus no main channel pip is available, only the upconverted sub channel can be inserted. the following functions are available in 4:1:1 only unless otherwise indicated: suitable for single pip, multi pip, replay and channel overview applications data formats 4 : 1 : 1 (all modes) and 4 :2:2 (some modes) pip osd for the sub channels displayed detection of pal/ntsc with overrule bit cte and lte like circuits in display part replay with definable auto increment, picture sample rate and picture number auto wrap programmable y*uv to rgb conversion matrix with independent coefficients for ntsc and pal sources display clock and synchronization are derived from the main channel pll. the following features are only available for the sub channel: sample rate of 14 mhz, 720 y* pixels/line horizontal reduction factors 1 1 1 2 , 1 3 , 1 4 and 1 6 vertical reduction factors 1 1 , 1 2 , 1 3 and 1 4 . 2f h ,1f v algorithms table 26 available 2fh and 1fv algorithms notes 1. median filtering in 4:2:2 mode is allowed for single pip (no main channel) and reduction factors not greater than 1 2 for both horizontal and vertical 2. the performance of the line doubling algorithm is dependent on the picture content. line (based interlace) flickering will remain in this mode. 2f h ,2f v algorithms table 27 available 2fh and 2fv algorithms note 1. median filtering in 4:2:2 mode is allowed for single pip (no main channel) and reduction factors not greater than 1 2 for both horizontal and vertical algorithm format 4 : 1 : 1 format 4 : 2 : 2 remarks progressive scan yes no; note 1 proscan (median ?ltering) line doubling yes yes note 2 algorithm format 4 : 1 : 1 format 4 : 2 : 2 remarks aabb ?eld doubling yes yes abab ?eld doubling yes yes abab ?elds interpolation via median ?ltering yes no; note 1 digital scan abab+ ?eld interpolation via median ?ltering and averaging with original ?elds yes no; note 1 digital scan plus
2000 jan 13 37 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs s lave 2f h and x f v related i 2 c- bus registers table 28 overview of the i 2 c-bus registers and their subaddresses d2fh and d2fv these bits control the display mode with respect to 2fh or 100 hz features. if d2fh is set to logic 1 the number of lines is doubled and/or if d2fv is set to logic 1 the number of fields is doubled. abmode these bits select the different algorithms for 2fh modes; see table 29. algorithm selection several display algorithms can be set with these bits; an overview is given in table 29. note: bgvfp the resolution of the mavfp bits changes in 2fh and xfv modes. in 2fh and 1fv modes the vertical resolution is 2 lines/field/step on 1fh base. in 2fh and 2fv modes the vertical resolution is 2 lines/field/step on 2fh base. table 29 overview of algorithm selection sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01h d2fh d2fv -- mfld (1:0) sfld (1:0) 02h yuvfilter (1:0) abmode (1:0) cte lte (2:0) mode d2fh yuvfilter d2fv abmode no ?lter 0 00h - 00h uv 1 : 1 v ?lter 0 01h 0 00h y 1 : 1 v ?lter 0 10h 0 00h yuv 1 : 1 v ?lter 0 11h 0 00h 2fh/1fv frame 1 xxh 0 00h 2fh/1fv proscan 1 xxh 0 01h 2fh/1fv line doubling 1 xxh 0 10h not valid 1 xxh 0 11h 2fh/2fv aabb 1 00h 1 00h 2fh/2fv abab 1 00h 1 01h 2fh/2fv abab 1 00h 1 10h 2fh/2fv abab+ 1 00h 1 11h
2000 jan 13 38 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs s lave 2f h memory requirements in the slave 2fh modes only the sub picture can be present. the following conditions must be met: when vertical reduction is 1, the field mode can be set to 3 when vertical reduction is not equal to 1, the field mode must be set to 4 when no live picture is present, such as replay or channel overview, the field mode can be set to 1. under these conditions a maximum number of stored fields/pictures can be determined. combined with the size of one picture, the total amount needed can be calculated always supposing that 1 pip is live. a selected overview is given in table 30. the vdram size is 262144 words of 16 bits table 30 memory requirements for 2fh slave s lave 2f h design restrictions the design has margins for a 2fh frequency of 31.5 khz. applying a svga source with a horizontal frequency of 38 khz will stress the SAB9079hs. therefore, a svga source can only be applied under the following restricted conditions: power supply spread of 5% instead of 10% no vcr like phase jump in 2fh signal. table 31 design characteristics note 1. the pll will lock within 20 lines to instable sources with a large phase jump if the frequency is within the range 28 to 36 khz. 2. the pll will lock to stable 2fh sources with a maximum frequency of 60 khz. mode pictures stored picture size ntsc (words) total ntsc picture size pal (words) total pal 2 v1_h2 4 46284 185136 56028 224112 4 v2_h2 7 23142 161994 28014 196098 6 v2_h3 9 15390 138510 18630 167670 9 v3_h3 12 10260 123120 12420 149040 12 v4_h3 15 7695 115425 9315 139725 16 v4_h4 19 5928 112632 7176 136344 symbol parameter conditions min. typ. max. unit supplies v ddd(p) all digital supply voltages for periphery 4.75 5.0 5.25 v v ddd(c) all digital supply voltages for core 3.15 3.3 3.6 v v dda all analog supply voltages 3.15 3.3 3.6 v v ss all ground voltages - 0 - v main pll and clock generation f i(pll) note 1 28 31.50 36 khz note 2 -- 60 khz
2000 jan 13 39 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs tv application with insertion after 100 h z ( slave ) in this application there is no relationship between the deflection and acquisition circuits. a double window feature can be realized by letting the feature box compress one window and make the second window by the SAB9079hs. in this application the hvsync of the feature box/line doubler is connected to the main acquisition hvsync. the restriction is that no main pips can be displayed. the application diagram is illustrated in fig.10. handbook, full pagewidth mgs830 y*uv display sub decoder hv hv decoder switch y*uv feature box/ line doubler hv y*uv (not used) hv y*uv/rgb fbl fig.10 2fh/1fh application with insertion after the feature box/line doubler. instead of the feature box a svga signal can be applied.
2000 jan 13 40 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs master 2fh general description a 1fh, 1fv signal at the acquisition side can be upconverted to a 2fh, 1fv or a 2fh, 2fv signal. the restriction is that both acquisition channels will be upconverted at the same time.therefore, the main channel displayed as 1fh, 1fv combined with a sub channel displayed as 2fh, 1fv is not possible. in the master mode the SAB9079hs generates the hsync and vsync for display/deflection. there is no protection built in. hsync and vsync cannot be coupled directly to a tube. a deflection ic should be applied. both main and sub pictures can be acquired/displayed. the following functions are available: suitable for single pip, some multi pip modes, replay and channel overview applications data formats 4 : 1 : 1 (all modes) and 4 :2:2 (some modes) sample rate of 14 mhz, 720 y* pixels/line horizontal reduction factors for main channel 1 1 3 4 , 2 3 , 1 2 , 1 3 , 1 4 and 1 6 horizontal reduction factors for sub channel 1 1 3 4 , 2 3 , 1 2 , 1 3 , 1 4 and 1 6 vertical reduction factors 1 1 , 1 2 , 1 3 and 1 4 . pip osd for the sub channels displayed detection of pal/ntsc with overrule bit cte and lte like circuits in display mode replay with definable auto increment, picture sample rate and picture number auto wrap programmable y*uv to rgb conversion matrix with independent coefficients for ntsc and pal sources display clock and synchronization are derived from the main channel pll. 2f h ,1f v algorithms table 32 available 2fh and 1fv algorithms notes 1. median filtering in 4:2:2 mode is allowed for single pip (no main channel) and reduction factors not greater than 1 2 for both horizontal and vertical 2. the performance of the line doubling algorithm is dependent on the picture content. line (based interlace) flickering will remain in this mode. 2f h ,2f v algorithms table 33 available 2fh and 2fv algorithms note 1. median filtering in 4:2:2 mode is allowed for single pip (no main channel) and reduction factors not greater than 1 2 for both horizontal and vertical algorithm format 4 : 1 : 1 format 4 : 2 : 2 remarks progressive scan yes no; note 1 proscan (median ?ltering) line doubling yes yes note 2 algorithm format 4 : 1 : 1 format 4 : 2 : 2 remarks aabb ?eld doubling yes yes abab ?eld doubling yes yes abab ?elds interpolation via median ?ltering yes no; note 1 digital scan abab+ ?eld interpolation via median ?ltering and averaging with original ?elds yes no; note 1 digital scan plus
2000 jan 13 41 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs m aster 2f h and x f v related i 2 c- bus registers table 34 overview of the i 2 c-bus registers and their subaddresses sub address data bytes bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 01h d2fh d2fv dmaster dvspos mfld (1:0) sfld (1:0) 02h yuvfilter (1:0) abmode (1:0) cte lte (2:0) 26h --- hswidth 27h -- vsdel 28h --- vswidth d2fh, d2fv, dmaster and dvspos these bits control the display mode with respect to 2fh or 100 hz features. if d2fh is set to logic 1 the number of lines is doubled and/or if d2fv is set to logic 1 the number of fields is doubled. if dmaster is at logic 0 the device is in slave mode. dhsync and dvsync should not be used. if dmaster is at logic 1 the device is in master mode which means that hv synchronization signals are generated. they are derived from mhsync and mvsync. the dhsync and dvsync output signals should be used as sync signals for the deflection ic. dvspos is only valid if dmaster is set to logic 1. if dvspos is set to logic 0 the vsync pulses are generated with an alternating field id according to the abab algorithm. if dvspos is set to logic 1 the vsync pulses are generated in the aabb scheme which means that two first fields are alternated with two second fields. abmode these bits select the different algorithms for 2fh modes; see table 35. hswidth the width of the dhsync can be set in the master mode. the width is from 0 to 31 pixels and the resolution is one 2fh pixel. vswidth the width of the dvsync can be set in the master mode. the scale is from 0 to 31 lines on a 2fh base and the resolution is 1 2 2fh. vsdel the position of the dvsync, with respect to the incoming mvsync, can be set in the master mode. the delay is a 6-bit value and the steps are from 0 to 63 lines on a 2fh base and the resolution is 1 2 2fh line. algorithm selection several display algorithms can be set with these bits; an overview is given in table 35. note: bgvfp the resolution of the bgvfp bits changes in 2fh and xfv modes. in 2fh and 1fv modes the vertical resolution is 2 lines/field/step on 1fh base. in 2fh and 2fv modes the vertical resolution is 2 lines/field/step on 2fh base.
2000 jan 13 42 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs table 35 overview of algorithm selection f ield mode settings in the master mode signals will be synchronized to the main 1fh, 1fv input signal. this eases the restrictions on the number of fields to be stored for the scan converted main picture. conditions to be met for a live picture are given in table 36. table 36 master 2fh ?eld mode settings mode d2fh yuvfilter d2fv abmode no ?lter 0 00h - 00h uv 1 : 1 v ?lter 0 01h 0 00h y 1 : 1 v ?lter 0 10h 0 00h yuv 1 : 1 v ?lter 0 11h 0 00h 2fh/1fv frame 1 xxh 0 00h 2fh/1fv proscan 1 xxh 0 01h 2fh/1fv line doubling 1 xxh 0 10h not valid 1 xxh 0 11h 2fh/2fv aabb 1 00h 1 00h 2fh/2fv abab 1 00h 1 01h 2fh/2fv abab 1 00h 1 10h 2fh/2fv abab+ 1 00h 1 11h vertical reduction fields for main channel fields for sub channel remarks 1/1 2 3 except for horizontal reduction 1/1 other modes 4 4 -
2000 jan 13 43 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs f eature box application 100 h z ( master ) in this mode the SAB9079hs generates the display clock which is derived from the main clock and synchronization signals. the whole system runs at one pll. only full screen images of the main decoder are handled. the pip insertion of the sub channel is not required here; see fig.11. d ouble window and / or other pip functions at 100 h z ( master ) this is the same configuration as fig.11 but the sub channel is also needed and, therefore, a second pll. the constraints apply with respect to the memory use and performance. double window pal is only possible if bit smlpal is set to logic 1, this is due to the memory limitations. d ouble window and / or other pip functions at 2f h ,1f v ( master ) for the application diagram please refer to fig.12. handbook, full pagewidth mgs831 y*uv (not used) display sub hv (not used) y*uv decoder deflection hv y*uv hv y*uv/rgb hv fig.11 100 hz application with eco-100 hz function. handbook, full pagewidth mgs832 y*uv display sub decoder hv y*uv decoder deflection hv y*uv hv y*uv/rgb hv fig.12 100 hz application with 2 channel pip function.
2000 jan 13 44 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs package outline unit a 1 min. a 2 a 3 b p ce (1) eh e ll p y w v q references outline version european projection issue date iec jedec eiaj mm 2.90 2.50 0.25 0.25 0.27 0.17 0.23 0.11 14.1 13.9 0.50 17.35 17.05 7 0 0.08 0.20 1.60 0.08 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.03 0.73 sot387-3 98-03-27 d (1) 20.1 19.9 h d 23.35 23.05 pin 1 index b p e q e a 1 a l p detail x l (a ) 3 b 38 c d h b p e h a 2 v m b d a e v m a 1 128 103 102 65 64 39 w m w m 0 5 10 mm scale sqfp128: plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 14 x 20 x 2.72 mm sot387-3 a max. 3.40 x y
2000 jan 13 45 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs soldering introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 jan 13 46 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 jan 13 47 philips semiconductors preliminary speci?cation multistandard picture-in-picture (pip) controller SAB9079hs definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 545004/50/01/pp 48 date of release: 2000 jan 13 document order number: 9397 750 05258

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